1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method. In particular, in photolithography processes among the manufacturing processes for semiconductor devices, it relates to a semiconductor device and a semiconductor device manufacturing method which improve the accuracy of alignment for achieving the optimum relative positional relationship between a pattern existing on a semiconductor substrate and a design pattern for the next process.
2. Description of the Prior Art
The development of super-high-integrated semiconductor devices has progressed in recent years. Along with this development, there is strong demand for further improvement in the alignment accuracy of masks in photolithography processes, which are essential to the formation of semiconductor elements, in order to promote further miniaturization and greater integration of semiconductor elements.
Conventionally, in the manufacture of a semiconductor device, patterns made up of films of various materials such as metal films, semiconductor films, insulating films or the like are sequentially stacked on a semiconductor substrate, and semiconductor elements with fine structures are formed. When stacking patterns for such semiconductor elements, in photolithography processes it is necessary to line up and form a next upper-layer pattern on top of a lower-layer pattern formed in a previous process.
In photolithography processes, a mask pattern is lined up with the lower-level pattern according to prescribed specifications when the photolithography process is performed for an upper-layer pattern. Higher alignment accuracy in the lining up of such patterns is required as semiconductor devices become increasingly fine and more highly integrated, and there is a need for techniques to raise alignment accuracy.
Alignment accuracy is generally calculated by forming a pair of box marks on the upper-layer pattern and lower-level pattern of a semiconductor chip, and measuring the misalignment between the box marks. For example, the relative position between a pair of box marks comprising some kind of mark formed on the semiconductor substrate and an alignment mark made of photoresist obtained through the photolithography process may be measured, and the dislocation in the relative position (amount of alignment dislocation) between the lower-layer pattern and the upper-layer pattern may be calculated by calculating the dislocation in the relative position therebetween. Alignment of the lower-layer pattern and upper-layer pattern is performed based on the amount of alignment dislocation.
Japanese Patent Laid-Open No. 9-232221, for example, discloses a semiconductor device and a semiconductor device manufacturing method whereby the relative position is calculated between an interlayer insulating film as a lower-layer pattern and a photoresist layer as an upper-layer pattern by measuring the relative position between a pair of box marks comprising a slit-shaped groove provided in a prescribed region of the interlayer insulating film and an alignment mark made of photoresist provided on a thin film stacked on the interlayer dielectric film.
Box marks used to detect alignment accuracy are provided on a region other than the region comprising elements such as transistors or the like. That is, as shown in FIG. 5, box mark formation regions 2, 3, 4, and 5 are formed on scribe lines 0, not on a chip region (product region) 1. By so doing, it is possible to calculate the amount of alignment dislocation without causing enlargement of the chip area. Moreover, since one box mark formation region is used for each alignment operation, the box mark formation regions used for each alignment operation are different. For this reason, it is necessary to have box alignment regions in at least a number equal to the number of times that alignment is performed.
Here, ease of viewing the box marks may be mentioned as one of the major elements influencing alignment accuracy when alignment of a lower-layer pattern and an upper-layer pattern is performed based on an amount of alignment dislocation calculated from the relative misalignment between box marks. FIG. 6 shows a process, in a conventional semiconductor device and semiconductor device manufacturing method, for forming box marks for alignment in a photolithography process for a conducting material film such as a poly-crystalline silicon layer or the like used as an electrode material in a DRAM. Here, as an example, description will be given in the case in which the box marks are formed in the box mark formation region 2 shown in FIG. 5.
As shown in FIG. 6(A), in a conventional semiconductor device and manufacturing method for a semiconductor device, an interlayer insulating film 27 is provided on a semiconductor substrate 26. The interlayer insulating film 27 is, for example, a film of SiO.sub.2, TEOSBPSG (Tetraethoxyorthosilicate Borophosphosilicate glass), or the like. The interlayer insulating film 27 comprises at least two layers or more of interlayer insulating film in the chip region (product region) so that a word line (not shown) made up of elements and a first poly-crystalline silicon layer and a bit line (not shown) made up of elements and a second poly-crystalline silicon layer will be mutually insulated therefrom. At this point, the interlayer insulating film 27 has a thickness of about 1000 nm or thereabouts. A word line and a bit line made up of a first poly-crystalline silicon layer and a second poly-crystalline silicon layer are formed in the chip region (product region) 1, but since no elements such as transistors or the like are formed in the box mark formation region, the word line, the bit line or the like made up of a first poly-crystalline silicon layer and a second poly-crystalline silicon layer is not formed in the box mark formation region 2. As shown in FIG. 6(A), a photoresist 28 is applied to the entire surface of the interlayer insulating film 27.
Next, as shown in FIGS. 6(B) and 6(C), using conventional photoresist techniques and etching techniques, a contact (not shown) for connecting a storage electrode made up of a conducting material film 210 of poly-crystalline silicon or the like is formed on an n.sup.- diffusion layer in the chip region (product region) 1, and at the same time, an opening groove 29-a is formed as a box mark in the box mark formation region 2 shown in FIG. 5. Next, after a conducting material film 210 about 500 to 700 nm thick, which is to become a storage electrode, is formed in the chip region (product region) 1 and box mark formation region 2, a photoresist 211 is applied to the entire surface, as shown in FIG. 6(D). Further, as shown in FIG. 6(E), an alignment mark 211-a is formed on the conducting material film 210 in the opening groove 29-a using conventionally-used photolithography techniques.
FIG. 6(F) shows a plan view corresponding to FIG. 6(E) Normally, the relative positional deviation of the alignment mark 211-a and the opening groove 29-a shown in FIG. 6(F) is mechanically calculated by applying existing image processing technology. Along with opening groove 29-a and alignment mark 211-a, FIG. 6(F) shows a waveform 212 showing measurement results data for the misalignment between opening groove 29-a and alignment mark 211-a obtained by existing image processing technology.
The conventional semiconductor device and conventional semiconductor manufacturing method shown in FIG. 6 have the following problems.
The conventional manufacturing method for semiconductor devices ordinarily includes a plurality of heat treatment processes. The heat treatment of an interlayer insulating film formed on a semiconductor substrate may be mentioned as representative of these.
When some kind of an interlayer insulating film (SiO.sub.2 or TEOSBPSG film or the like) is formed on a semiconductor substrate, the interlayer insulating film which is formed will have irregularities on the surface, and will not be flat. For this reason, in order to obtain sufficient flatness in ordinary manufacturing methods for semiconductor devices, flattening is performed by performing heat treatment of the interlayer insulating film and causing reflow (fluidization). At this time, the interlayer insulating film is sufficiently flattened by performing heat treatment at or above the prescribed temperature for causing reflow (fluidization) of the interlayer insulating film. It is further known that if an interlayer insulating film has been caused to reflow once, reflow will not occur again if the temperature does not rise above the temperature (reflow temperature) at the time when the interlayer insulating film was caused to reflow.
Since in conventional semiconductor devices, the semiconductor elements were not that miniature and the level integration was also low, even if the temperature for heat processing with the purpose of flattening the interlayer insulating film was fairly high there was little effect on the device characteristics or semiconductor devices. However, along with the recent miniaturization and greater integration of semiconductor devices, in cases where a high temperature is used as the temperature (reflow temperature) for heat processing when performing flattening, there is a comparatively large effect on device characteristics and semiconductor elements in comparison to conventional semiconductor devices. Therefore, when performing heat processing with the purpose of flattening an interlayer insulating film, a need has arisen to perform the heat processing at as low a temperature as possible within the temperature range at which it is possible to perform sufficient flattening of the interlayer insulating film. Thus the heat processing performed when carrying out flattening has come to be performed at a relatively low reflow temperature in comparison to conventional practice. However, a problem has arisen in that while flattening has come to be performed in this way at temperatures comparatively lower than the conventional practice, the heat treatment temperatures used in processes other than flattening of the interlayer insulating film have risen.
For example, in a semiconductor device and manufacturing method for semiconductor devices as shown in FIG. 6, when heat treatment is applied (for example, under a N.sub.2 atmosphere at 850.degree. C. for 10 min.) with the purpose of activating ions injected by an ion injection method following heat treatment at 800.degree. C. (reflow temperature) with the purpose of flattening an interlayer insulating film 27, which is made of SiO.sub.2 or TEOSBPSG film or the like, the temperature (850.degree. C.) of the heat treatment process with the purpose of activating the ions is higher than the reflow temperature (800.degree. C.) of the interlayer insulating film 27. This causes deformation of the shape of the interlayer insulating film 27 from the vicinity of the bottom of the side surfaces of the opening groove 29-a to the bottom, because the interlayer insulating film 27 is made to reflow again (re-fluidize). The degree of change in shape of the edge part of the opening groove 29-a (part from the vicinity of the bottom of the sides of the edge groove 29-a to the bottom) is proportional to the volume of the interlayer insulating film 27 adjacent to the outer sides of the opening groove 29-a. That is, since the remaining width a"1 is larger in comparison to the remaining width a"2, as shown in FIG. 6(F), the volume of the interlayer insulating film 27 adjacent to the side of the remaining width a"1 will be larger than on the side of the remaining width a"2. For this reason, there is a greater degree of change in shape in the edge part of the opening groove 29-a on the side of the remaining width a"1 compared to the edge part on the side of the remaining width a"2, so that it takes on a shape that intrudes into the conducting material film 210 to be formed later. For this reason, when measuring the amount of misalignment of the alignment mark 211-a and the opening groove 29-a using existing image processing technology, the peak at the edge part of the remaining width a"1 of the opening groove becomes less sharply defined in the waveform 212 of the data showing the misalignment measurement results, as shown in FIG. 6(F). As a result, a problem arises in that it becomes difficult to accurately read the relative amount of alignment dislocation between box marks (between the alignment mark 211-a and the opening groove 29-a), so that the alignment accuracy between the lower-layer pattern and upper-layer pattern falls remarkably.